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1 for more information www.linear.com/ltc2376-20 typical application features description 20-bit, 250ksps, low power sar adc with 0.5ppm inl the lt c ? 2376-20 is a low noise, low power, high speed 20-bit successive approximation register (sar) adc. op- erating from a 2.5v supply, the ltc2376-20 has a v ref fully differential input range with v ref ranging from 2.5v to 5.1v. the ltc2376-20 consumes only 5.3mw and achieves 2ppm inl maximum, no missing codes at 20 bits with 104db snr. the ltc2376-20 has a high speed spi-compatible serial interface that supports 1.8v, 2.5v, 3.3v and 5v logic while also featuring a daisy-chain mode. the fast 250ksps throughput with no cycle latency makes the ltc2376-20 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time , easing exter - nal timing considerations. the ltc2376-20 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate. the ltc2376-20 features a unique digital gain compres- sion ( dgc) function , which eliminates the driver amplifier s negative supply while preserving the full resolution of the adc. when enabled, the adc performs a digital scaling function that maps zero-scale code from 0v to 0.1 ? v ref and full-scale code from v ref to 0.9 ? v ref . for a typical reference voltage of 5v, the full-scale input range is now 0.5v to 4.5v, which provides adequate headroom for powering the driving amplifier from a single 5.5v supply. integral nonlinearity vs output code applications n 250ksps throughput rate n 0.5ppm inl (typ) n guaranteed 20-bit no missing codes n low power: 5.3mw at 250ksps, 5.3w at 250sps n 104db snr (typ) at f in = 2khz n C125db thd (typ) at f in = 2khz n digital gain compression (dgc) n guaranteed operation to 85c n 2.5v supply n fully differential input range v ref n v ref input range from 2.5v to 5.1v n no pipeline delay, no cycle latency n 1.8v to 5v i/o voltages n spi-compatible serial i/o with daisy-chain mode n internal conversion clock n 16-lead msop and 4mm 3mm dfn packages n medical imaging n high speed data acquisition n portable or compact instrumentation n industrial process control n low power battery-operated instrumentation n ate output code 0 262144 524288 786432 1048576 ?2.0 inl error (ppm) 0.5 1.0 1.5 0 ?0.5 ?1.0 ?1.5 2.0 237620 ta02 10 v ref 0v v ref 0v 10 3300pf 6800pf 6800pf ? + v ref sample clock 237620 ta01 10f 0.1f 2.5v ref 1.8v to 5v 2.5v to 5.1v 47f (x7r, 1210 size) ref gnd chain rdl/sdi sdo sck busy cnv ref/dgc ltc2376-20 v dd ov dd in + in ? l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. protected by u.s. patents, including 7705765, 7961132, 8319673. ltc2376 -20 237620fa
2 for more information www.linear.com/ltc2376-20 pin configuration absolute maximum ratings supply voltage ( v dd ) ............................................... 2.8 v supply voltage ( ov dd ) ................................................ 6 v reference input ( ref ) ................................................. 6 v analog input voltage ( note 3) in + , in C ......................... ( gnd C 0.3 v ) to ( ref + 0.3 v ) ref / dgc input ( note 3) .... ( gnd C 0.3 v ) to ( ref + 0.3 v ) digital input voltage ( note 3) .......................... ( gnd C 0.3 v ) to ( ov dd + 0.3 v ) (notes 1, 2) 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 gnd ov dd sdo sck rdl/sdi busy gnd cnv chain v dd gnd in + in ? gnd ref ref/ dgc top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 40c/w exposed pad (pin 17) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 chain v dd gnd in + in ? gnd ref ref/ dgc 16 15 14 13 12 11 10 9 gnd ov dd sdo sck rdl/sdi busy gnd cnv top view ms package 16-lead plastic msop t jmax = 150c, ja = 110c/w order information lead free finish tape and reel part marking* package description temperature range ltc2376cms-20#pbf ltc2376cms-20#trpbf 237620 16-lead plastic msop 0c to 70c ltc2376ims-20#pbf ltc2376ims-20#trpbf 237620 16-lead plastic msop C40c to 85c ltc2376cde-20#pbf ltc2376cde-20#trpbf 23760 16-lead (4mm 3mm) plastic dfn 0c to 70c ltc2376ide-20#pbf ltc2376ide-20#trpbf 23760 16-lead (4mm 3mm) plastic dfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ digital output voltage ( note 3) .......................... ( gnd C 0.3 v ) to ( ov dd + 0.3 v ) power dissipation .............................................. 500 mw operating temperature range ltc 2376 c ................................................ 0 c to 70 c ltc 2376 i ............................................. C40 c to 85 c storage temperature range .................. C65 c to 150 c ltc2376 -20 237620fa
3 for more information www.linear.com/ltc2376-20 dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 2khz, v ref = 5v l 101 104 db snr signal-to-noise ratio f in = 2khz, v ref = 5v f in = 2khz, v ref = 5v, ref/dgc = gnd f in = 2khz, v ref = 2.5v l l l 101 99 95.5 104 102 98 db db db thd total harmonic distortion f in = 2khz, v ref = 5v f in = 2khz, v ref = 5v, ref/dgc = gnd f in = 2khz, v ref = 2.5v l l l C125 C125 C123 C115 C114 C113 db db db sfdr spurious free dynamic range f in = 2khz, v ref = 5v l 115 128 db C3db input bandwidth 34 mhz aperture delay 500 ps aperture jitter 4 ps transient response full-scale step 1 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 8) electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C0.1 v ref + 0.1 v v in C absolute input range (in C ) (note 5) l C0.1 v ref + 0.1 v v in + C v in C input differential voltage range v in = v in + C v in C l Cv ref +v ref v v cm common-mode input range l v ref /2C 0.1 v ref /2 v ref /2+ 0.1 v i in analog input leakage current 0.01 a c in analog input capacitance sample mode hold mode 45 5 pf pf cmrr input common mode rejection ratio f in = 125khz 86 db the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) converter characteristics symbol parameter conditions min typ max units resolution l 20 bits no missing codes l 20 bits transition noise 2.3 ppm rms inl integral linearity error (note 6) ref/dgc = gnd, (note 6) l l C2 C2 0.5 0.5 2 2 ppm ppm dnl differential linearity error (note 10) l C0.5 0.2 0.5 ppm bze bipolar zero-scale error (note 7) l C13 0 13 ppm bipolar zero-scale error drift 7 ppb/c fse bipolar full-scale error (note 7) l C100 10 100 ppm bipolar full-scale error drift 0.05 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) ltc2376 -20 237620fa
4 for more information www.linear.com/ltc2376-20 adc timing characteristics symbol parameter conditions min typ max units f smpl maximum sampling frequency l 250 ksps t conv conversion time l 2 3 s t acq acquisition time t acq = t cyc C t hold (note 10) l 3.312 s t hold maximum time between acquisitions l 688 ns t cyc time between conversions l 4 s t cnvh cnv high time l 20 ns t busylh cnv to busy delay c l = 20pf l 13 ns t cnvl minimum low time for cnv (note 11) l 20 ns t quiet sck quiet time from cnv (note 10) l 20 ns t sck sck period (notes 11, 12) l 10 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) power requirements symbol parameter conditions min typ max units v dd supply voltage l 2.375 2.5 2.625 v ov dd supply voltage l 1.71 5.25 v i vdd i ovdd i pd supply current supply current power down mode 250ksps sample rate 250ksps sample rate (c l = 20pf) conversion done (i vdd + i ovdd + i ref ) l l 2.1 0.1 1 2.5 90 ma ma a p d power dissipation power down mode 250ksps sample rate conversion done (i vdd + i ovdd + i ref ) 5.25 2.5 6.25 225 mw w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) reference input symbol parameter conditions min typ max units v ref reference voltage (note 5) l 2.5 5.1 v i ref reference input current (note 9) l 0.24 0.3 ma v ihdgc high level input voltage ref/dgc pin l 0.8v ref v v ildgc low level input voltage ref/dgc pin l 0.2v ref v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) ltc2376 -20 237620fa
5 for more information www.linear.com/ltc2376-20 adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units t sckh sck high time l 4 ns t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 11) l 4 ns t hsdisck sdi hold time from sck (note 11) l 1 ns t sckch sck period in chain mode t sckch = t ssdisck + t dsdo (note 11) l 13.5 ns t dsdo sdo data valid delay from sck c l = 20pf, ov dd = 5.25v c l = 20pf, ov dd = 2.5v c l = 20pf, ov dd = 1.71v l l l 7.5 8 9.5 ns ns ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 10) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 10) l 5 ns t en bus enable time after rdl (note 11) l 16 ns t dis bus relinquish time after rdl (note 11) l 13 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may effect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above ref or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above ref or ov dd without latch-up. note 4: v dd = 2.5v, ov dd = 2.5v, ref = 5v, v cm = 2.5v, f smpl = 250khz, ref/dgc = v ref . note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero- scale error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 0000 and 1111 1111 1111 1111 1111. full- scale bipolar error is the worst- case of C fs or + fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error . note 8: all specifications in db are referred to a full-scale 5v input with a 5v reference voltage. note 9: f smpl = 250khz, i ref varies proportionately with sample rate. note 10: guaranteed by design, not subject to test. note 11: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 12: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising capture. 0.8*ov dd 0.2*ov dd 50% 50% 237620 f01 0.2*ov dd 0.8*ov dd 0.2*ov dd 0.8*ov dd t delay t width t delay figure 1. voltage levels for timing specifications ltc2376 -20 237620fa
6 for more information www.linear.com/ltc2376-20 frequency (khz) snr, sinad (dbfs) 108 237620 g05 92 94 96 98 100 102 106 104 0 25 50 75 100 125 snr sinad frequency (khz) harmonics, thd (dbfs) ?90 237620 g06 ?140 ?120 ?130 ?110 ?100 ?125 ?135 ?115 ?105 ?95 0 25 50 100 75 125 3rd 2nd thd typical performance characteristics 128k point fft f s = 250ksps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs reference voltage , f in = 2khz thd, harmonics vs reference voltage , f in = 2khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram output code 0 262144 524288 786432 1048576 ?2.0 inl error (ppm) 0.5 1.0 1.5 0 ?0.5 ?1.0 ?1.5 2.0 237620 g01 frequency (khz) 0 25 50 75 125 100 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237620 g04 snr = 104db thd = ?128db sinad = 104db sfdr = 132db output code ?0.5 dnl error (ppm) 0.4 0.3 0.2 0.1 0.0 ?0.4 ?0.3 ?0.2 ?0.1 0.5 237620 g02 0 262144 524288 786432 1048576 output code 524295 524291 524287 524283 524279 0 counts 20000 10000 5000 45000 30000 25000 15000 35000 40000 50000 237620 g03 = 2.3 t a = 25c, v dd = 2.5v, ov dd = 2.5v, v cm = 2.5v, ref = 5v, f smpl = 250ksps, unless otherwise noted. input level (db) snr, sinad (dbfs) 105.0 237620 g07 103.0 103.5 104.0 104.5 ?40 ?30 ?20 ?10 0 snr sinad reference voltage (v) snr, sinad (dbfs) 105 104 103 102 237620 g08 95 96 97 98 99 100 101 2.5 3.0 3.5 4.0 4.5 5.0 sinad snr harmonics, thd (dbfs) ?110 237620 g09 ?140 ?135 ?130 ?125 ?120 ?115 3rd reference voltage (v) 2.5 3.0 3.5 4.0 4.5 5.0 2nd thd ltc2376 -20 237620fa
7 for more information www.linear.com/ltc2376-20 snr, sinad vs temperature, f in = 2khz thd, harmonics vs temperature, f in = 2khz typical performance characteristics supply current vs temperature shutdown current vs temperature cmrr vs input frequency reference current vs reference voltage inl vs temperature full-scale error vs temperature offset error vs temperature t a = 25c, v dd = 2.5v, ov dd = 2.5v, v cm = 2.5v, ref = 5v, f smpl = 250ksps, unless otherwise noted. frequency (khz) 0 5025 75 100 125 70 cmrr (db) 85 80 75 100 95 90 237620 g17 0 reference current (ma) 0.2 0.1 0.3 237620 g18 reference voltage (v) 2.5 3.0 3.5 4.0 4.5 5.0 temperature (c) snr, sinad (dbfs) 106 105 104 103 237620 g10 100 101 102 ?55 ?35 ?15 5 25 45 65 85 105 125 sinad snr temperature (c) harmonics, thd (dbfs) ?120 237620 g11 ?140 ?135 ?130 ?125 ?55 ?35 ?15 5 25 6545 85 105 125 thd 2nd 3rd temperature (c) inl error (ppm) 2.0 237620 g12 ?2.0 ?1.0 ?1.5 ?0.5 0 1.5 1.0 0.5 ?55 25 45 65 ?35 ?15 5 85 105 125 max inl min inl temperature (c) full-scale error (ppm) 20 237620 g13 ?20 0 10 5 15 ?10 ?5 ?15 ?55 ?35 25 45 65 ?15 5 85 105 125 ?fs +fs temperature (c) power supply current (ma) 2.5 2.0 237620 g15 0 0.5 1.0 1.5 ?55 ?35 ?15 5 25 45 65 85 105 125 i vdd i ref i ovdd temperature (c) offset error (ppm) 4 3 2 1 237620 g14 ?4 ?2 0 ?1 ?3 ?55 ?35 ?15 255 45 65 85 105 125 temperature (c) power-down current (a) 45 40 35 30 237620 g16 0 5 10 15 20 25 ?50 ?25 0 25 50 75 100 125 i vdd + i ovdd + i ref ltc2376 -20 237620fa
8 for more information www.linear.com/ltc2376-20 chain (pin 1): chain mode selector pin. when low, the ltc2376-20 operates in normal mode and the rdl/sdi input pin functions to enable or disable sdo. when high, the ltc2376-20 operates in chain mode and the rdl/sdi pin functions as sdi, the daisy-chain serial data input. logic levels are determined by ov dd . v dd (pin 2): 2.5v power supply. the range of v dd is 2.375v to 2.625v . bypass v dd to gnd with a 10f ceramic capacitor . gnd (pins 3, 6, 10 and 16): ground. in + , in C (pins 4, 5): positive and negative differential analog inputs. ref (pin 7): reference input. the range of ref is 2.5v to 5.1v . this pin is referred to the gnd pin and should be decoupled closely to the pin with a 47f ceramic capacitor (x7r, 1210 size, 10v rating). ref/dgc (pin 8): when tied to ref, digital gain compres- sion is disabled and the ltc2376-20 defines full-scale ac- cording to the v ref analog input range. when tied to gnd, digital gain compression is enabled and the ltc2376 - 20 defines full-scale with inputs that swing between 10% and 90% of the v ref analog input range. cnv (pin 9): convert input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by ov dd . busy (pin 11): busy indicator . goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by ov dd . rdl/sdi (pin 12): when chain is low, the part is in nor - mal mode and the pin is treated as a bus enabling input. when chain is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another adc in the daisy chain is input. logic levels are determined by ov dd . sck ( pin 13): serial data clock input. when sdo is enabled , the conversion result or daisy-chain data from another adc is shifted out on the rising edges of this clock msb first. logic levels are determined by ov dd . sdo (pin 14): serial data output. the conversion result or daisy-chain data is output on this pin on each rising edge of sck msb first. the output data is in 2s complement format. logic levels are determined by ov dd . ov dd (pin 15): i/o interface digital power. the range of ov dd is 1.71v to 5.25v . this supply is nominally set to the same supply as the host interface (1.8v, 2.5v, 3.3v, or 5v). bypass ov dd to gnd with a 0.1f capacitor . gnd (exposed pad pin 17 C dfn package only): ground. exposed pad must be soldered directly to the ground plane . pin functions ltc2376 -20 237620fa
9 for more information www.linear.com/ltc2376-20 functional block diagram ref = 2.5v to 5.1v in + v dd = 2.5v ov dd = 1.8v to 5v in ? chain cnv gnd busy ref/dgc sdo sck rdl/sdi control logic 20-bit sampling adc spi port + ? 237620 bd01 ltc2376 -20 237620fa
10 for more information www.linear.com/ltc2376-20 timing diagram applications information power-down convert acquire hold d17 d19 d18 d2 d1 d0 sdo sck cnv chain, rdl/sdi = 0 busy 237620 td01 conversion timing using the serial interface overview the ltc2376-20 is a low noise, low power, high speed 20-bit successive approximation register (sar) adc. operating from a single 2.5v supply, the ltc2376-20 supports a large and flexible v ref fully differential input range with v ref ranging from 2.5v to 5.1v, making it ideal for high performance applications which require a wide dynamic range. the ltc2376-20 achieves 2ppm inl maximum, no missing codes at 20 bits and 104db snr. fast 250ksps throughput with no cycle latency makes the ltc2376-20 ideally suited for a wide variety of high speed applications. an internal oscillator sets the con- version time, easing external timing considerations. the ltc2376 - 20 dissipates only 5.3mw at 250ksps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. the ltc2376-20 features a unique digital gain compres- sion ( dgc) function , which eliminates the driver amplifier s negative supply while preserving the full resolution of the adc. when enabled, the adc performs a digital scaling function that maps zero-scale code from 0v to 0.1 ? v ref and full-scale code from v ref to 0.9 ? v ref . for a typical reference voltage of 5v, the full-scale input range is now 0.5v to 4.5v, which provides adequate headroom for powering the driving amplifier from a single 5.5v supply. converter operation the ltc2376-20 operates in two phases. during the ac- quisition phase, the charge redistribution capacitor d/a converter (cdac) is connected to the in + and in C pins to sample the differential analog input voltage. a rising edge on the cnv pin initiates a conversion. during the conversion phase , the 20- bit cdac is sequenced through a successive approximation algorithm , effectively comparing the sampled input with binary -weighted fractions of the reference voltage (e.g. v ref /2, v ref /4 v ref /1048576) using the differential comparator . at the end of conversion , the cdac output approximates the sampled analog input. the adc control logic then prepares the 20-bit digital output code for serial transfer . transfer function the ltc2376-20 digitizes the full-scale voltage of 2 ref into 2 20 levels, resulting in an lsb size of 9.5v with ref = 5 v . note that 1 lsb at 20 bits is approximately 1ppm. the ideal transfer function is shown in figure 2. the output data is in 2s complement format. analog input the analog inputs of the ltc2376-20 are fully differential in order to maximize the signal swing that can be digitized. the analog inputs can be modeled by the equivalent circuit ltc2376 -20 237620fa
11 for more information www.linear.com/ltc2376-20 shown in figure 3. the diodes at the input provide esd protection. in the acquisition phase, each input sees ap- proximately 45pf (c in ) from the sampling cdac in series with 40? ( r on ) from the on-resistance of the sampling switch. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the adc. the inputs draw a current spike while charging the c in capacitors during acquisition. during conversion, the analog inputs draw only a small leakage current. input drive circuits a low impedance source can directly drive the high imped- ance inputs of the ltc2376-20 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize adc linearity. for best performance , a buffer amplifier should be used to drive the analog inputs of the ltc2376-20. the amplifier provides low output impedance , which produces fast settling of the analog applications information figure 2. ltc2376-20 transfer function input voltage (v) 0v output code (two?s complement) ?1 lsb 237620 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/1048576 1ppm signal during the acquisition phase. it also provides isola- tion between the signal source and the adc input currents. noise and distortion the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise . the simple 1- pole rc lowpass filter ( lpf 1) shown in figure 4 is sufficient for many applications. r on 40 c in 45pf r on 40 ref ref c in 45pf in + in ? bias voltage 237620 f03 figure 3. the equivalent circuit for the differential analog input of the ltc2376-20 a coupling filter network (lpf2) should be used between the buffer and adc input to minimize disturbances reflected into the buffer from sampling transients. long rc time constants at the analog inputs will slow down the settling of the analog inputs. therefore, lpf2 typically requires a wider bandwidth than lpf1. this filter also helps minimize the noise contribution from the buffer. a buffer amplifier with a low noise density must be selected to minimize degradation of the snr. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering . metal film surface mount resistors are much less susceptible to both problems. input currents one of the biggest challenges in coupling an amplifier to the ltc2376-20 is in dealing with current spikes drawn by the adc inputs at the start of each acquisition phase. 10 3300pf 6600pf 10 500 lpf2 lpf1 bw = 1.2mhz bw = 48khz single-ended- to-differential driver single-ended- input signal ltc2376-20 in + in ? 237620 f04 6800pf 6800pf figure 4. input signal chain ltc2376 -20 237620fa
12 for more information www.linear.com/ltc2376-20 applications information the adc inputs may be modeled as a switched capacitor load of the drive circuit . a drive circuit may rely partially on attenuating switched-capacitor current spikes with small filter capacitors (c filt ) placed directly at the adc inputs, and partially on the driver amplifier having suffi- cient bandwidth to recover from the residual disturbance. amplifiers optimized for dc performance may not have sufficient bandwidth to fully recover at the adc s maximum conversion rate, which can produce nonlinearity and other errors. coupling filter circuits may be classified in three broad categories: fully settled C this case is characterized by filter time constants and an overall settling time that is consider - ably shorter than the sample period. when acquisition begins, the coupling filter is disturbed. for a typical first order rc filter, the disturbance will look like an initial step with an exponential decay. the amplifier will have its own response to the disturbance, which may include ringing. if the input settles completely (to within the accuracy of the ltc 2376 -20), the disturbance will not contribute any error . partially settled C in this case, the beginning of acquisition causes a disturbance of the coupling filter, which then begins to settle out towards the nominal input voltage. however, acquisition ends (and the conversion begins) before the input settles to its final value. this generally produces a gain error, but as long as the settling is linear, no distortion is produced. the coupling filters response is affected by the amplifiers output impedance and other parameters. a linear settling response to fast switched- capacitor current spikes can not always be assumed for precision, low bandwidth amplifiers. the coupling filter serves to attenuate the current spikes high-frequency energy before it reaches the amplifier. fully averaged C if the coupling filter capacitors ( c filt ) at the adc inputs are much larger than the adc s sample capacitors (45pf), then the sampling glitch is greatly attenuated. the driving amplifier effectively only sees the average sampling current , which is quite small . at 250 ksps , the equivalent input resistance is approximately 89k ( as shown in figure 5 ), a benign resistive load for most precision amplifiers . however , resistive voltage division will occur between the coupling filter s dc resistance and the adc s equivalent ( switched- capacitor) input resistance, thus producing a gain error. the input leakage currents of the ltc2376-20 should also be considered when designing the input drive circuit , because source impedances will convert input leakage currents to an added input voltage error. the input leakage currents , both common mode and differential , are typically extremely small over the entire operating temperature range. figure 6 shows input leakage currents over tem- perature for a typical part. figure 5. equivalent circuit for the differential analog input of the ltc2376-20 at 250ksps. figure 6. common mode and differential input leakage current over temperature ltc2376-20 bias voltage in + in ? c filt >> 45pf 237620 f05 r eq r eq c filt >> 45pf r eq = 1 f smpl ? 45pf temperature (c) input leakage (na) 30 237620 f06 ?10 0 10 20 ?55 ?35 ?15 5 25 6545 85 differential v in = v ref common let r s1 and r s2 be the source impedances of the dif- ferential input drive circuit shown in figure 7, and let i l1 and i l2 be the leakage currents flowing out of the adcs analog inputs. the voltage error, v e , due to the leakage currents can be expressed as: v e = r s1 + r s2 2 ? i l1 Ci l2 ( ) + r s1 Cr s2 ( ) ? i l1 + i l2 2 ltc2376 -20 237620fa
13 for more information www.linear.com/ltc2376-20 applications information figure 8. lt6203 buffering a fully differential signal source lt6203 237620 f08 0v 5v 0v 5v 5 7 6 + ? 0v 5v 3 1 2 + ? 0v 5v as shown in figure 8 can be used to get the full data sheet distortion performance of C125db. single-ended-to-differential conversion for single - ended input signals , a single - ended - to - differential conversion circuit must be used to produce a differential signal at the inputs of the ltc2376-20. the lt6203 adc driver is recommended for performing single-ended-to-differential conversions. the lt6203 is flexible and may be configured to convert single-ended signals of various amplitudes to the 5v differential input range of the ltc2376-20. figure 9a shows the lt6203 being used to convert a 0v to 5 v single - ended input signal . in this case, the first amplifier is configured as a unity gain buffer and the single-ended figure 7. source impedances of a driver and input leakage currents of the ltc2376-20 the common mode input leakage current, (i l1 + i l2 )/2, is typically extremely small (figure 6) over the entire operat- ing temperature range and common mode input voltage range. thus, any reasonable mismatch (below 5%) of the source impedances r s 1 and r s 2 will cause only a negligible error. the differential input leakage current , (i l1 C i l2 ), depends on temperature and is maximum when v in = v ref , as shown in figure 6. the differential leakage current is also typically very small, and its nonlinear component is even smaller. only the nonlinear component will impact the adcs linearity. for optimal performance , it is recommended that the source impedances, r s1 and r s2 , be between 10 and 50 and with 1% tolerance. for source impedances in this range, the voltage and temperature coefficients of r s1 and r s2 are usually not critical. the guaranteed ac and dc specifications are tested with 10 source imped- ances, and the specifications will gradually degrade with increased source impedances due to incomplete settling of the inputs. fully differential inputs a low distortion fully differential signal source driven through the lt6203 configured as two unity gain buffers r s1 r s2 i l1 i l2 237620 f07 in + v e in ? + ? ltc2376-20 lt6203 v cm = ref/2 237620 f09a 0v 5v 0v 5v out2 499 499 249 out1 3 7 1 5 6 2 + ? + ? ? + 0v 5v 10f frequency (khz) 0 25 50 75 100 125 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237620 f09b snr = 104db thd = ?121.4db sinad = 103.9db sfdr = 122.1db figure 9a. lt6203 converting a 0v to 5v single- ended signal to a 5v differential input signal figure 9b. 128k point fft plot with f in = 2khz for circuit shown in figure 9a ltc2376 -20 237620fa
14 for more information www.linear.com/ltc2376-20 applications information input signal directly drives the high- impedance input of the amplifier. as shown in the fft of figure 9b, the lt6203 drives the ltc 2376 -20 to near full data sheet performance . digital gain compression the ltc2376-20 offers a digital gain compression (dgc) feature which defines the full-scale input swing to be be- tween 10% and 90% of the v ref analog input range. to enable digital gain compression, bring the ref/dgc pin low. this feature allows the sar adc driver to be powered off of a single positive supply since each input swings between 0.5v and 4.5v as shown in figure 10. needing only one positive supply to power the sar adc driver results in additional power savings for the entire system. with dgc enabled, the ltc2376-20 can be driven by the low power ltc6362 differential driver which is powered from a single 5 v supply . figure 11a shows how to configure the ltc6362 to accept a 3.28v true bipolar single-ended input signal and level shift the signal to the reduced input range of the ltc2376-20 when digital gain compression is enabled. when paired with the ltc6655-4.096 for the reference, the entire signal chain solution can be powered from a single 5v supply, minimizing power consump- tion and reducing complexity. as shown in the fft of figure ?11 b, the single 5v supply solution can achieve up to 100db of snr. dc accuracy many driver circuits presented in this data sheet em- phasize ac performance ( distortion and signal-to-noise ratio), and the amplifiers are chosen accordingly. the very low level of distortion is a direct consequence of the excellent inl of the ltc2376-20, and this property can be exploited in dc applications as well. note that while the ltc6362 and lt6203 are characterized by excellent ac specifications, their dc specifications do not match those of the ltc2376-20. the offset of these amplifiers, for example, is more than 500v under certain conditions. in contrast, the ltc2376-20 has a guaranteed maximum offset error of 130v (typical drift 0.007ppm/c), and a guaranteed maximum full-scale error of 100ppm (typical drift 0.05ppm/c). low drift is important to maintain ac- curacy over wide temperature ranges in a calibrated system. amplifiers have to be selected very carefully to provide a 20-bit accurate dc signal chain. a large-signal open-loop gain of at least 126db may be required to ensure 1 ppm linearity for amplifiers configured for a gain of negative figure 10. input swing of the ltc2376 with gain compression enabled 237620 f10 5v 4.5v 0.5v 0v ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237620 f11b snr = 100db thd = ?110db sinad = 99.7db sfdr = 113db frequency (khz) 0 25 50 75 100 125 figure 11b. 64k point fft plot with f in = 2khz for circuit shown in figure 11a figure 11a. ltc6362 configured to accept a 3.28v input signal while running from a single 5v supply when digital gain compression is enabled in the ltc2376-20 237620 f11a 1k v cm v ? 5 4 2 6 v + 3 8 1 2 1k 1k 35.7 3300pf 35.7 1k 1k v cm 1k 0.41v 3.69v 0.41v 3.69v 4.096v 5v 47f 10f ltc2376-20 ref/dgc in + ref v dd 2.5v in ? ltc6655-4.096 v in v out_s v out_f ?3.28v 3.28v 0v 6800pf 6800pf ? + ltc6362 ltc2376 -20 237620fa
15 for more information www.linear.com/ltc2376-20 1. however, less gain is sufficient if the amplifiers gain characteristic is known to be (mostly) linear. an ampli- fiers offset versus signal level must be considered for amplifiers configured as unity gain buffers. for example, 1ppm linearity may require that the offset is known to vary less than 5v for a 5v swing. however, greater offset variations may be acceptable if the relationship is known to be (mostly) linear. unity-gain buffer amplifiers typically require substantial headroom to the power supply rails for best performance . inverting amplifier circuits configured to minimize swing at the amplifier input terminals may perform better with only little headroom than unity-gain buffer amplifiers. the linearity and thermal properties of an inverting amplifiers feedback network should be considered carefully to ensure dc accuracy. adc reference the ltc2376-20 requires an external reference to define its input range. a low noise, low temperature drift refer - ence is critical to achieving the full data sheet performance of the adc. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power and high accuracy, the ltc6655-5 is particularly well suited for use with the ltc2376-20. the ltc6655-5 offers 0.025% (max) initial accuracy and 2ppm/c (max) temperature coefficient for high precision applications. when choosing a bypass capacitor for the ltc6655-5, the capacitors voltage rating, temperature rating, and pack- age size should be carefully considered. physically larger capacitors with higher voltage and temperature ratings tend to provide a larger effective capacitance, better filtering the noise of the ltc6655-5, and consequently producing a higher snr. therefore, we recommend bypassing the ltc6655-5 with a 47f ceramic capacitor (x7r , 1210 size, 10v rating) close to the ref pin. applications information the ref pin of the ltc 2376 -20 draws charge ( q conv ) from the 47f bypass capacitor during each conversion cycle. the reference replenishes this charge with a dc current, i ref = q conv /t cyc . the dc current draw of the ref pin, i ref , depends on the sampling rate and output code. if the ltc2376-20 is used to continuously sample a signal at a constant rate, the ltc6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5lsbs. when idling, the ref pin on the ltc2376-20 draws only a small leakage current (< 1 a). in applications where a burst of samples is taken after idling for long periods as shown in figure 12, i ref quickly goes from approximately 0a to a maximum of 0.3ma at 250ksps. this step in dc current draw triggers a transient response in the reference that must be considered since any deviation in the refer - ence output voltage will affect the accuracy of the output code. in applications where the transient response of the reference is important, the fast settling ltc6655-5 refer - ence is also recommended. dynamic performance fast fourier transform ( fft ) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm , the adc s spectral content can be examined for frequencies outside the fundamental. the ltc 2376-20 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling cnv idle period idle period 237620 f12 figure 12. cnv waveform showing burst sampling ltc2376 -20 237620fa
16 for more information www.linear.com/ltc2376-20 applications information frequency. figure 13 shows that the ltc2376-20 achieves a typical sinad of 104db at a 250khz sampling rate with a 2khz input. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and power considerations the ltc2376-20 provides two power supply pins: the 2.5v power supply (v dd ), and the digital input/ output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2376-20 to communicate with any digital logic operating between 1.8v and 5v, including 2.5v and 3.3v systems. power supply sequencing the ltc2376-20 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2376 - 20 has a power-on-reset (por) circuit that will reset the ltc2376-20 at initial power-up or whenever the power supply voltage drops below 1v. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 200s after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control cnv timing the ltc2376-20 conversion is controlled by cnv . a ris- ing edge on cnv will start a conversion and power up the ltc2376-20. once a conversion has been initiated, it cannot be restarted until the conversion is complete. for optimum performance , cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40ns from the start of the conversion or after the conversion has been completed. acquisition a proprietary sampling architecture allows the ltc 2376 -20 to begin acquiring the input signal for the next conver - sion 675ns after the start of the current conversion . this figure 13. 128k point fft plot with f in = 2khz of the ltc2376-20 frequency (khz) 0 25 50 75 125 100 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237620 f13 snr = 104db thd = ?128db sinad = 104db sfdr = 132db the rms amplitude of all other frequency components except the first five harmonics and dc. figure 13 shows that the ltc2376-20 achieves a typical snr of 104db at a 250khz sampling rate with a 2khz input. total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself . the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v1 is the rms amplitude of the fundamental fre - quency and v 2 through v n are the amplitudes of the second through nth harmonics. ltc2376 -20 237620fa
17 for more information www.linear.com/ltc2376-20 applications information extends the acquisition time to 3.312s, easing settling requirements and allowing the use of extremely low power adc drivers. (refer to the timing diagram.) internal conversion clock the ltc2376-20 has an internal clock that is trimmed to achieve a maximum conversion time of 3s. auto power-down the ltc2376 -20 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of cnv. during power down, data from the last conversion can be clocked out. to minimize power dissipation during power down, disable sdo and turn off sck. the auto power-down feature will reduce the power dissipation of the ltc2376-20 as the sampling frequency is reduced. since power is consumed only during a conversion, the ltc 2376 -20 remains powered - down for a larger fraction of the conversion cycle (t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 14. digital interface the ltc2376-20 has a serial digital interface . the flexible ov dd supply allows the ltc2376-20 to communicate with any digital logic operating between 1.8v and 5v, including 2.5v and 3.3v systems. the serial output data is clocked out on the sdo pin when an external clock is applied to the sck pin if sdo is enabled . clocking out the data after the conversion will yield the best performance . with a shift clock frequency of at least 20mhz, a 250ksps throughput is still achieved. the serial output data changes state on the rising edge of sck and can be captured on the falling edge or next rising edge of sck. d19 remains valid until the first rising edge of sck. the serial interface on the ltc2376-20 is simple and straightforward to use . the following sections describe the operation of the ltc2376-20. several modes are provided depending on whether a single or multiple adcs share the spi bus or are daisy chained. sampling rate (khz) 0 250 150 200 50 100 0 power supply current (ma) 2.5 2.0 1.5 1.0 0.5 237620 f14 i vdd i ref i ovdd figure 14. power supply current of the ltc2376-20 versus sampling rate ltc2376 -20 237620fa
18 for more information www.linear.com/ltc2376-20 timing diagrams normal mode, single device when chain = 0, the ltc2376-20 operates in normal mode. in normal mode, rdl/sdi enables or disables the serial data output pin sdo. if rdl/sdi is high, sdo is in high impedance. if rdl/sdi is low, sdo is driven. figure 15 shows a single ltc2376-20 operated in normal mode with chain and rdl/sdi tied to ground. with rdl/ sdi grounded, sdo is enabled and the msb(d19) of the new conversion data is available at the falling edge of busy . this is the simplest way to operate the ltc 2376 -20. cnv ltc2376-20 busy convert irq data in digital host clk sdo sck 237620 f15a rdl/sdi chain 237620 f15 convert convert t acq t acq = t cyc ? t hold power-down power-down cnv chain = 0 busy sck sdo rdl/sdi = 0 t busylh t dsdobusyl t sck t hsdo t sckh t quiet t sckl t dsdo t conv t cnvh t hold acquire t cyc t cnvl d19 d18 d17 d1 d0 1 2 3 18 19 20 acquire figure 15. using a single ltc2376-20 in normal mode ltc2376 -20 237620fa
19 for more information www.linear.com/ltc2376-20 timing diagrams normal mode, multiple devices figure 16 shows multiple ltc2376-20 devices operating in normal mode (chain = 0) sharing cnv, sck and sdo. by sharing cnv, sck and sdo, the number of required signals to operate multiple adcs in parallel is reduced. since sdo is shared, the rdl/sdi input of each adc must be used to allow only one ltc2376-20 to drive sdo at a time in order to avoid bus conflicts. as shown in figure 16, the rdl/sdi inputs idle high and are individually brought low to read data out of each device between conversions. when rdl/sdi is brought low, the msb of the selected device is output onto sdo. 237620 f16a rdl b rdl a convert irq data in digital host clk cnv ltc2376-20 sdo a sck rdl/sdi cnv ltc2376-20 sdo b sck rdl/sdi chain busy chain 237620 f16 d19 a sdo sck cnv busy chain = 0 rdl/sdi b rdl/sdi a d19 b d18 b d1 b d0 b d17 b d18 a d17 a d1 a d0 a hi-z hi-z hi-z t en t hsdo t dsdo t dis t sckl t sckh t cnvl 1 2 3 18 19 20 21 22 23 38 39 40 t sck convert convert t quiet t conv t hold t busylh power-down acquire acquire power-down figure 16. normal mode with multiple devices sharing cnv, sck and sdo ltc2376 -20 237620fa
20 for more information www.linear.com/ltc2376-20 timing diagrams ov dd 237620 f17a convert irq data in digital host clk cnv ltc2376-20 busy sdo b sck rdl/sdi cnv ltc2376-20 sdo a sck rdl/sdi chain ov dd chain chain mode, multiple devices when chain = ov dd , the ltc2376-20 operates in chain mode. in chain mode, sdo is always enabled and rdl/sdi serves as the serial data input pin (sdi) where daisy-chain data output from another adc can be input. this is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. figure 17 shows an example with two daisy-chained devices. the msb of converter a will appear at sdo of converter b after 20 sck cycles. the msb of converter a is clocked in at the sdi/rdl pin of converter b on the rising edge of the first sck. 237620 f17 d0 a d1 a d18 a d19 a d17 b d18 b d19 b sdo b sdo a = rdl/sdi b rdl/sdi a = 0 d0 b d1 b d17 a d18 a d19 a d0 a d1 a 1 2 3 18 19 20 21 22 38 39 40 t dsdobusyl t ssdisck t hsdisck t busylh t conv t hold t hsdo t dsdo t sckl t sckh t sckch t cnvl t cyc convert convert sck cnv busy chain = ov dd t quiet power-down power-down acquire acquire figure 17. chain mode timing diagram ltc2376 -20 237620fa
21 for more information www.linear.com/ltc2376-20 to obtain the best performance from the ltc2376-20 a printed circuit board is recommended. layout for the printed circuit board (pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layout the following is an example of a recommended pcb layout . a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1925a, the evaluation kit for the ltc2376-20. top silkscreen board layout ltc2376 -20 237620fa
22 for more information www.linear.com/ltc2376-20 board layout layer 1 component side ltc2376 -20 237620fa
23 for more information www.linear.com/ltc2376-20 layer 2 ground plane board layout ltc2376 -20 237620fa
24 for more information www.linear.com/ltc2376-20 board layout layer 3 pwr plane ltc2376 -20 237620fa
25 for more information www.linear.com/ltc2376-20 layer 4 bottom layer board layout ltc2376 -20 237620fa
26 for more information www.linear.com/ltc2376-20 board layout partial schematic of demoboard c68 15pf cog c58 1f 25v bypass capacitors for u10 v + c42 0.1f 25v r54 opt c67 opt c18 10f 6.3v r55 0 1 2 3 ac dc jp7 coupling ac dc jp8 coupling c66 opt c69 10f 6.3v c70 opt r56 opt c47 0.1f 25v c19 0.1f 25v 1 2 3 j4 bnc j2 bnc r53 0 a in + 0 ? v ref a in ? 0 ? v ref u6 nc7sz66p5x c13 0.1f 4 1 2 9 cnv sck c20 47f 10v 1206 x7r c56 0.1f cnv ref gnd gnd gnd gnd ref/dgc v dd v ref 0.8v ref ov dd sck sdo busy rdl/sdi sdo busy rd ltc2376-20 in ? in + 5 4 3 2 1 5 4 13 14 11 12 b a 5 3 gnd v cc oe +3.3v r5 49.9 1206 r6 1k u8 nc7sz04p5x u2 nc7svu04p5x u15 ltc6655ahms8-5 u3 nl17sz74 u4 nc7svu04p5x cnvst_33 from cpld clk to cpld c5 0.1f c1 0.1f c11 0.1f shdn gnd gnd out_f gnd gnd 9v to 10v 1 2 3 4 8 7 6 5 +3.3v +3.3v +3.3v 3 42 5 3 42 5 c2 0.1f r3 33 r2 1k r1 33 +3.3v +3.3v 3 1 4 6 2 8 7 5 r8 33 c3 0.1f r15 33 c4 0.1f v in out_s gnd v cc clr\ q\ cp q d pr\ 3 4 2 5 +3.3v dc590 detect to cpld +3.3v u9 nc7sz04p5x c15 0.1f c16 0.1f 3 4 2 5 +3.3v r13 1k r17 2k r10 4.99k u7 24lc025-i/st r11 4.99k r12 4.99k c14 0.1f 6 8 4 237620 bl 5 7 3 2 1 scl sda array eeprom wp a2 a1 a0 v ss v cc 1 3 5 7 9 11 13 2 4 6 8 10 12 14 j3 dc590 sdo sck cnv 9v to 10v r7 1k 10 16 6 3 1 15 7 2 8 jp6 fs 1 2 3 hd1x3-100 opt c7 0.1f c6 10f 6.3v +2.5v c10 0.1f c71 6800pf npo c72 3300pf 1206 npo r51 10 c73 6800pf npo c9 10f 6.3v r9 0 r4 0 r48 10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 db19 1 3 5 7 11 9 13 15 17 19 21 23 25 27 29 31 33 35 37 39 p1 40 42 44 46 48 50 52 54 db18 db17 db16 clkout clk2 41 43 45 47 49 51 53 55 clk in j1 v + v ? r46 0 r44 opt c76 opt ? + r45 opt u10a lt6203ms8 c65 opt 5 6 7 r49 opt r50 0 r52 0 r58 opt c75 opt ? + r47 opt u10b lt6203ms8 u18b lt6203ms8 c39 opt r39 0 7 5 6 + ? r38 249 r34 499 c62 10f 6.3v r40 opt c59 10f 6.3v c60 10f 6.3v c77 0.1f 25v c45 0.1f 25v r36 opt r35 opt r80 2k 0603 edge-con-100 3.3v c64 opt r33 499 c63 opt 3 2 1 5 4 v + v ? r41 0 ? + r30 0 u18a lt6203ms8 c61 opt r57 opt jp4 cm e5 ext_cm 1 2 3 v ref/2 v ref ext c8 1f c74 1f 25v r18 249 3 2 1 5 4 v + v ? ? + r88 1 u5 lt6202cs8 r86 499k c78 4.7f 6.3v r87 499k c40 1f 25v c17 1f 25v v ? c55 1f 25v bypass capacitors for u18 v + c57 0.1f 25v c48 0.1f 25v c43 0.1f 25v c49 1f 25v c44 1f 25v v ? 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 94 96 98 100 db2 db1 db0 95 97 99 r81 4.99k ltc2376 -20 237620fa
27 for more information www.linear.com/ltc2376-20 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de16) dfn 0806 rev ? pin 1 notch r = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc2376 -20 237620fa
28 for more information www.linear.com/ltc2376-20 msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc2376 -20 237620fa
29 for more information www.linear.com/ltc2376-20 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 03/15 corrected a typo in the schematic of figure 11a and typical application 14 and 30 ltc2376 -20 237620fa
30 for more information www.linear.com/ltc2376-20 ? linear technology corporation 2013 lt 0315 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2376-20 related parts typical application part number description comments adcs ltc2378-20 20-bit, 1msps, 0.5ppm inl serial, low power adc 2.5v supply, 5v fully differential input, 104db snr, msop-16 and 4mm 3mm dfn-16 packages ltc2379-18/ltc2378-18 ltc2377-18/ltc2376-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380 -16/ltc2378-16 ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2369-18/ltc2368-18/ ltc2367-18/ltc2364-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 96.5db snr, 0v to 5v input range, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2370-16/ltc2368-16 ltc2367-16/ltc2364-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 94db snr, 0v to 5v input range, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2383-16/ltc2382-16/ ltc2381-16 16-bit, 1msps/500ksps/250ksps, low power adc 2.5v supply, differential input, 92db snr, 2.5v input range, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages dacs ltc2756/ltc2757 18-bit, single serial/parallel i out softspan? dac 1lsb inl/dnl, ssop-28 and 7mm 7mm lqfp-48 packages ltc2641 16-/14-/12-bit single serial v out dac 1lsb inl /dnl, msop-8 package, 0v to 5v output ltc2630 12-/10-/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references ltc6655 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers ltc6362 low power rail-to-rail input/output differential output amplifier/adc driver single 2.8v to 5.25v supply, 1ma supply current, msop-8 and 3mm 3mm dfn-8 packages lt6200 /lt6200-5/ lt6200-10 165mhz/800mhz/1.6ghz op amp with unity gain/av = 5/av = 10 low noise voltage: 0.95nv/hz (100khz), low distortion: C80db at 1mhz, tsot23-6 package lt6202/lt6203 single/dual 100mhz rail-to-rail input/output noise low power amplifiers 1.9nvhz, 3ma maximum, 100mhz gain bandwidth, tsot23-5, so-8 , msop-8 and 3mm 3mm dfn-8 packages ltc6362 configured to accept a 3.28v input signal while running from a single 5v supply with digital gain compression enabled in the ltc2376-20 237620 ta03 1k v cm v ? 5 4 6 v + 3 8 1 2 1k 1k 35.7 3300pf 35.7 1k 1k v cm 1k 0.41v 3.69v 0.41v 3.69v 4.096v 5v 47f 10f ltc2376-20 ref/dgc in + ref v dd 2.5v in ? ltc6655-4.096 v in v out_s v out_f ?3.28v 3.28v 6800pf 6800pf ? + ltc6362 0v ltc2376 -20 237620fa

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